Method for forming gate structure of three-dimensional memory device

ABSTRACT

A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming an alternating dielectric stack on a substrate; forming multiple slits, each penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing multiple sacrificial layers in the alternating dielectric stack through the plurality of slits to form multiple trenches; forming a conductive layer in each of the trenches; forming a first isolation layer on sidewalls of the slits to cover the conductive layers to prevent the conductive layers from being oxidized; forming a second isolation layer on surfaces of the first isolation layer, a material of the second isolation layer being different from a material of the first isolation layer; and depositing a conductive material into the slits to form multiple conductive walls, the conductive walls are insulated from the conductive layers.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to PCT/CN2018/089839 filed on Jun. 4,2018, which claims priority to Chinese Patent Application No.201710729505.5 filed on Aug. 23, 2017, the entire contents of which areincorporated herein by reference.

BACKGROUND

Embodiments of the present disclosure relate to three-dimensional (3D)memory devices and fabrication methods thereof.

Planar memory cells are scaled to smaller sizes by improving processtechnology, circuit design, programming algorithm, and fabricationprocess. However, as feature sizes of the memory cells approach a lowerlimit, planar process and fabrication techniques become challenging andcostly. As a result, memory density for planar memory cells approachesan upper limit.

A 3D memory architecture can address the density limitation in planarmemory cells. The 3D memory architecture includes a memory array andperipheral devices for controlling signals to and from the memory array.

BRIEF SUMMARY

Embodiments of method for forming gate structures of 3D memory devicesand fabrication methods thereof are disclosed herein.

Disclosed is a method for forming a three-dimensional (3D) NAND memorydevice, comprising: forming, on a substrate, an alternating dielectricstack including a plurality of dielectric layer pairs, each of theplurality of dielectric layer pairs comprising a first dielectric layerand a second dielectric layer different from the first dielectric layer;forming a plurality of slits, each penetrating vertically through thealternating dielectric stack and extending in a horizontal direction;removing the plurality of second dielectric layers in the alternatingdielectric stack through the plurality of slits to form a plurality oftrenches; forming a conductive layer in each of the plurality oftrenches; forming a first isolation layer on sidewalls of the pluralityof slits to cover the conductive layers to prevent the conductive layersfrom being oxidized; forming a second isolation layer on surfaces of thefirst isolation layer, a material of the second isolation layer beingdifferent from a material of the first isolation layer; and depositing aconductive material into the slits to form a plurality of conductivewalls, wherein the plurality of conductive walls are insulated from theconductive layers.

In some embodiments, each of the plurality of dielectric layer pairs isformed of a silicon oxide layer having a thickness in a range from about10 nm to about 150 nm and a silicon nitride layer having a thickness ina range from about 10 nm to about 150 nm.

In some embodiments, the method further comprises: forming a pluralityof channel structures, each penetrating vertically through thealternating dielectric stack; wherein each of the plurality of slitsextends horizontally between the plurality of channel structures.

In some embodiments, the method further comprises: after forming theplurality of slits, forming a plurality of doped regions below the slitsin the substrate, so as to contact each conductive wall with acorresponding doped region.

In some embodiments, the method further comprises: forming a filmincluding silicon, silicon nitride, silicon oxynitride, or aluminumoxide as the first isolation layer, a thickness of the film being in arange from about 0.1 nm to about 10 nm.

In some embodiments, the method further comprises: forming a siliconfilm as the first isolation layer; forming a silicon oxide film as thesecond isolation layer and; and oxidizing at least a portion of thesilicon film to silicon oxide during forming the second isolation layer.

In some embodiments, forming the plurality of channel structurescomprises: forming a channel hole extending vertically through thealternating dielectric stack; forming a functional layer on a sidewallof the channel hole; and forming a channel layer covering a sidewall ofthe functional layer.

In some embodiments, forming the functional layer comprises: forming abarrier layer on the sidewall of the channel hole for blocking anoutflow of the electronic charges; forming a storage layer on thesurface of the barrier layer for storing electronic charges duringoperation of the 3D memory device; and forming a tunneling layer on thesurface of the storage layer for tunneling electronic charges.

In some embodiments, the method further comprises: before forming theconductive layer in the plurality of trenches, forming an insulatinglayer in the plurality of trenches.

In some embodiments, forming the insulating layer comprises: forming afirst insulating sub-layer covering top surfaces and bottom surfaces ofthe plurality of first dielectric layers, and outside sidewall portionsof functional layers that are exposed by the plurality of trenches; andforming a second insulating sub-layer having a thickness in a range fromabout 1 nm to about 10 nm to cover the first insulating sub-layer.

In some embodiments, the first insulating sub-layer is formed bydepositing a first material including aluminum oxide; and the secondinsulating sub-layer is formed by depositing a second material includingtitanium nitride.

In some embodiments, the method further comprises: before forming theinsulating layer, performing a phosphoric acid rinsing process to cleanthe plurality of trenches, wherein a rinsing temperature of thephosphoric acid rinsing process is in a range from about 100° C. toabout 200° C., and a rinsing time of the phosphoric acid rinsing processis in a range from about 10 minutes to about 100 minutes.

In some embodiments, forming the conductive layer comprises: filling theplurality of trenches with a conductive material; and removing portionsof the conductive material to form a plurality of separated gates, eachof the plurality of separated gates being locating in a correspondingtrench.

In some embodiments, forming the first isolation layer comprises:performing a polyatomic layer chemical vapor deposition process or anatomic layer deposition process to form first isolation layer.

In some embodiments, forming the first isolation layer comprises:forming the first isolation layer to cover the sidewalls of theplurality of slits, exposed surfaces of the insulating layer, andexposed surfaces of the conductive layers.

In some embodiments, forming the first isolation layer comprises:forming the first isolation layer having a plurality of recesses, eachcorresponding to a separated gate.

In some embodiments, forming the alternating dielectric stack comprises:forming the alternating dielectric stack having a thickness larger than1000 nm in a vertical direction.

In some embodiments, forming the plurality of conductive wallscomprises: depositing a material including tungsten into the pluralityof slits to form the plurality of conductive walls.

Another aspect of the present disclosure provides a three-dimensional(3D) NAND memory device, comprising: an alternatingdielectric/conductive stack including a plurality ofdielectric/conductive layer pairs on a substrate, each of the pluralityof dielectric/conductive layer pairs comprising a dielectric layer and aconductive layer; a plurality of slits, each penetrating verticallythrough the alternating dielectric/conductive stack and extending in ahorizontal direction; a first isolation layer on sidewalls of theplurality of slits to cover the conductive layers to prevent theconductive layers from being oxidized; a second isolation layer onsurfaces of the first isolation layer, a material of the secondisolation layer being different from a material of the first isolationlayer; and a conductive wall sandwiched by the second isolation layer ineach slit, wherein the conductive wall is insulated from the conductivelayers of the alternating dielectric/conductive stack.

In some embodiments, each of the dielectric layer is a silicon oxidelayer having a thickness in a range from about 10 nm to about 150 nm;each of the conductive layer is a tungsten layer having a thickness in arange from about 10 nm to about 150 nm; and the conductive wall includestungsten.

In some embodiments, the device further comprises: a plurality ofchannel structures, each penetrating vertically through the alternatingdielectric/conductive stack; wherein each of the plurality of slitsextends horizontally between the plurality of channel structures.

In some embodiments, the device further comprises: a plurality of dopedregions below the slits in the substrate, wherein the conductive wall isin contact with a corresponding doped region in each slit.

In some embodiments, the first isolation layer is a film includingsilicon, silicon nitride, silicon oxynitride, or aluminum oxide; and thesecond isolation layer is a silicon oxide film.

In some embodiments, a thickness of the first isolation layer is in arange from about 0.1 nm to about 10 nm.

In some embodiments, each of the plurality of channel structurescomprises: a channel hole extending vertically through the alternatingdielectric/conductive stack; a functional layer on a sidewall of thechannel hole; and a channel layer covering a sidewall of the functionallayer.

In some embodiments, the functional layer comprises: a barrier layer onthe sidewall of the channel hole configured to block an outflow of theelectronic charges; a storage layer on the surface of the barrier layerconfigured to store electronic charges during operation of the 3D memorydevice; and a tunneling layer on the surface of the storage layerconfigured to tunnel electronic charges.

In some embodiments, the device further comprises: an insulating layerbetween the each dielectric layer and each conductive layer.

In some embodiments, the insulating layer is between the conductivelayers and the functional layer.

In some embodiments, the insulating layer comprises: a first insulatingsub-layer covering top surfaces and bottom surfaces of the plurality ofdielectric layers, and outside sidewall portions of functional layer;and a second insulating sub-layer covering the first insulatingsub-layer and having a thickness in a range from about 1 nm to about 10nm.

In some embodiments, the first insulating sub-layer includes aluminumoxide; and the second insulating sub-layer includes titanium nitride.

In some embodiments, the first isolation layer having a plurality ofrecesses, each corresponding to a conductive layer sandwiched betweentwo dielectric layers.

In some embodiments, the alternating dielectric/conductive stack has atleast 64 dielectric/conductive layer pairs and has a thickness largerthan 1000 nm in a vertical direction.

Other aspects of the present disclosure can be understood by thoseskilled in the art in light of the description, the claims, and thedrawings of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated herein and form a partof the specification, illustrate embodiments of the present disclosureand, together with the description, further serve to explain theprinciples of the present disclosure and to enable a person skilled inthe pertinent art to make and use the present disclosure.

FIG. 1 illustrates a schematic cross-sectional view of an exemplary 3Dmemory device according to some fabricating methods.

FIG. 2 illustrates a flow diagram of an exemplary method for forming agate structure of a 3D memory device, according to some embodiments ofthe present disclosure.

FIGS. 3A-3G illustrate schematic cross-sectional views of an exemplary3D memory device at certain fabricating stages of the method shown inFIG. 2 according to some embodiments of the present disclosure.

Embodiments of the present disclosure will be described with referenceto the accompanying drawings.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, itshould be understood that this is done for illustrative purposes only. Aperson skilled in the pertinent art will recognize that otherconfigurations and arrangements can be used without departing from thespirit and scope of the present disclosure. It will be apparent to aperson skilled in the pertinent art that the present disclosure can alsobe employed in a variety of other applications.

Various embodiments in accordance with the present disclosure provide agate-last process for forming a gate structure of a 3D memory device. Inthe disclosed method, after forming a multi-layer gate structure, andbefore forming an isolation layer (e.g. a silicon oxide layer) on thesidewall of slits, an additional isolation layer (e.g. a silicon film)can be formed to cover the exposed surfaces of the multi-layer gatestructure to prevent the exposed surfaces of the multi-layer gatestructure from being oxidized during the deposition of the silicon oxidelayer. As such, a leakage between the multi-layer gate structure andconductive wall in the slit can be eliminated.

It is noted that references in the specification to “one embodiment,”“an embodiment,” “an example embodiment,” “some embodiments,” etc.,indicate that the embodiment described may include a particular feature,structure, or characteristic, but every embodiment may not necessarilyinclude the particular feature, structure, or characteristic. Moreover,such phrases do not necessarily refer to the same embodiment. Further,when a particular feature, structure or characteristic is described inconnection with an embodiment, it would be within the knowledge of aperson skilled in the pertinent art to effect such feature, structure orcharacteristic in connection with other embodiments whether or notexplicitly described.

In general, terminology may be understood at least in part from usage incontext. For example, the term “one or more” as used herein, dependingat least in part upon context, may be used to describe any feature,structure, or characteristic in a singular sense or may be used todescribe combinations of features, structures or characteristics in aplural sense. Similarly, terms, such as “a,” “an,” or “the,” again, maybe understood to convey a singular usage or to convey a plural usage,depending at least in part upon context.

It should be readily understood that the meaning of “on,” “above,” and“over” in the present disclosure should be interpreted in the broadestmanner such that “on” not only means “directly on” something but alsoincludes the meaning of “on” something with an intermediate feature or alayer therebetween, and that “above” or “over” not only means themeaning of “above” or “over” something but can also include the meaningit is “above” or “over” something with no intermediate feature or layertherebetween (i.e., directly on something).

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper,” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

As used herein, the term “substrate” refers to a material onto whichsubsequent material layers are added. The substrate itself can bepatterned. Materials added on top of the substrate can be patterned orcan remain unpatterned. Furthermore, the substrate can include a widearray of semiconductor materials, such as silicon, germanium, galliumarsenide, indium phosphide, etc. Alternatively, the substrate can bemade from an electrically non-conductive material, such as a glass, aplastic, or a sapphire wafer.

As used herein, the term “layer” refers to a material portion includinga region with a thickness. A layer can extend over the entirety of anunderlying or overlying structure, or may have an extent less than theextent of an underlying or overlying structure. Further, a layer can bea region of a homogeneous or inhomogeneous continuous structure that hasa thickness less than the thickness of the continuous structure. Forexample, a layer can be located between any pair of horizontal planesbetween, or at, a top surface and a bottom surface of the continuousstructure. A layer can extend horizontally, vertically, and/or along atapered surface. A substrate can be a layer, can include one or morelayers therein, and/or can have one or more layer thereupon, thereabove,and/or therebelow. A layer can include multiple layers. For example, aninterconnection layer can include one or more conductor and contactlayers (in which contacts, interconnect lines, and/or vias are formed)and one or more dielectric layers.

As used herein, the term “nominal/nominally” refers to a desired, ortarget, value of a characteristic or parameter for a component or aprocess operation, set during the design phase of a product or aprocess, together with a range of values above and/or below the desiredvalue. The range of values can be due to slight variations inmanufacturing processes or tolerances. As used herein, the term “about”indicates the value of a given quantity that can vary based on aparticular technology node associated with the subject semiconductordevice. Based on the particular technology node, the term “about” canindicate a value of a given quantity that varies within, for example,10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

As used herein, the term “3D memory device” refers to a semiconductordevice with vertically-oriented strings of memory cell transistors(i.e., region herein as “memory strings,” such as NAND strings) on alaterally-oriented substrate so that the memory strings extend in thevertical direction with respect to the substrate. As used herein, theterm “vertical/vertically” means nominally perpendicular to a lateralsurface of a substrate.

FIG. 1 illustrates a schematic cross-sectional view of an exemplary 3Dmemory device according to some fabricating methods. In some fabricatingmethods, the gate-last process can include depositing multiple siliconnitride layers as dummy gate layers. Multiple silicon oxide layers areformed to isolate the multiple dummy gate layers. Multiple silts areformed by an etching process. Multiple horizontal trenches are formed byetching the multiple silicon nitride layers to remove dummy gate layers.A multi-layer gate structure is formed by a metal depositing process. Afurther etching process is performed to separate multiple metal gates. Asilicon oxide layer is formed on the sidewalls of the multiple slits.And a metal wall is disposed as an array common source (ACS) in eachslit, and metal contacts are formed.

In some fabricating methods, the metal gates are easily oxidized togenerate metal whiskers during subsequent deposition processes forforming silicon oxide layers. As shown in FIG. 1, the generated metalwhisker 110 can grow close to the silicon oxide layer on the sidewall ofthe ACS, or even penetrate the silicon oxide layer on the sidewall ofthe ACS, causing leakage between the metal gates and the metal wall inthe slit. That is, the existing fabricating methods may result inproduct failure.

Accordingly, the present disclosure provides a gate-last process forforming a gate structure of a 3D memory device. In the disclosedgate-last process, a silicon film with a moderate thickness can beformed between the metal gates and the silicon oxide layer on thesidewall of the slits. The silicon film can act as a protective layer toeffectively prevent the metal gates from being oxidized to whiskers anddirectly contacting with the metal wall in the slit, so as to ensure thenormal function of the product.

FIG. 2 illustrates a flow diagram of an exemplary method for forming agate structure of a 3D memory device, according to some embodiments ofthe present disclosure. FIGS. 3A-3G illustrate schematic cross-sectionalviews of an exemplary 3D memory device at certain fabricating stages ofthe method shown in FIG. 2 according to some embodiments of the presentdisclosure.

As shown in FIG. 2, the method starts at operation S2, in which analternating dielectric stack is formed on a substrate. In someembodiments, the substrate can be any suitable semiconductor substratehaving any suitable structure, such as a monocrystalline single-layersubstrate, a polycrystalline silicon (polysilicon) single-layersubstrate, a polysilicon and metal multi-layer substrate, etc.

As shown in FIG. 3A, an alternating dielectric stack 200 including aplurality of dielectric layer pairs can be formed on the substrate 100.Each dielectric layer pairs of the alternating dielectric stack 200 caninclude an alternating stack of a first dielectric layer 210 and asecond dielectric layer 220 that is different from first dielectriclayer 210. In some embodiments, the first dielectric layers 210 can beused as insulating layers, and the second dielectric layer 220 can beused as sacrificial layers, which are to be removed in the subsequentprocesses.

The plurality of first dielectric layers 210 and second dielectriclayers 220 are extended in a lateral direction that is parallel to asurface of the substrate 100. In some embodiments, there are more layersthan the dielectric layer pairs made of different materials and withdifferent thicknesses in the alternating dielectric stack 200. Thealternating dielectric stack 200 can be formed by one or more thin filmdeposition processes including, but not limited to, Chemical VaporDeposition (CVD), Physical Vapor Deposition (PVD), Atomic LayerDeposition (ALD), or any combination thereof

In some embodiments, the alternating dielectric stack 200 can include aplurality of oxide/nitride layer pairs. Each dielectric layer pairincludes a layer of silicon oxide 210 and a layer of silicon nitride220. The plurality of oxide/nitride layer pairs are also referred toherein as an “alternating oxide/nitride stack.” That is, in thealternating dielectric stack 200, multiple oxide layers 210 and multiplenitride layers 220 alternate in a vertical direction. In other words,except a top and a bottom layer of a given alternating oxide/nitridestack, each of the other oxide layers 210 can be sandwiched by twoadjacent nitride layers 220, and each of the nitride layers 220 can besandwiched by two adjacent oxide layers 210.

Oxide layers 210 can each have the same thickness or have differentthicknesses. For example, a thickness of each oxide layer can be in arange from about 10 nm to about 150 nm. Similarly, nitride layers 220can each have the same thickness or have different thicknesses. Forexample, a thickness of each nitride layer can be in a range from about10 nm to about 150 nm. In some embodiments, a total thickness of thealternating dielectric stack 200 can be larger than 1000 nm.

It is noted that, in the present disclosure, the oxide layers 210 and/ornitride layers 220 can include any suitable oxide materials and/ornitride materials. For example, the element of the oxide materialsand/or nitride materials can include, but not limited to, tungsten (W),cobalt (Co), copper (Cu), aluminum (Al), doped silicon, silicides, orany combination thereof. In some embodiments, the oxide layers can besilicon oxide layers, and the nitride layers can be silicon nitridelayer.

The alternating dielectric stack 200 can include any suitable number oflayers of the oxide layers 210 and the nitride layers 220. In someembodiments, a total number of layers of the oxide layers 210 and thenitride layers 220 in the alternating dielectric stack 200 is equal toor larger than 64. That is, a number of oxide/nitride layer pairs can beequal to or larger than 32. In some embodiments, alternatingoxide/nitride stack includes more oxide layers or more nitride layerswith different materials and/or thicknesses than the oxide/nitride layerpair. For example, a bottom layer and a top layer in the alternatingdielectric stack 200 can be oxide layers 210.

As shown in FIG. 2, the method proceeds to operation S4, in whichmultiple channel structures can be formed in the alternating dielectricstack. Each channel structure can include a channel hole 300 extendingvertically through the alternating dielectric stack 200, a functionallayer 310 on the sidewall of the channel hole 300, and a channel layer320 between the functional layer and a filling structure 330. Themultiple channel structures can be arranged as an array in thealternating dielectric stack 200. For example, a number of the multiplechannel structures can be 1, 2², 3², . . . , (1+n)², where n is aninteger large than 1.

In some embodiments, fabrication processes to form the channel structureinclude forming a channel hole 300 that extends vertically through thealternating dielectric stack 200. The channel hole 300 can have a highaspect ratio, and can be formed by etching the alternating dielectricstack 200, and a subsequent cleaning process. The etching process toform the channel hole 300 can be a wet etching, a dry etching, or acombination thereof

In some embodiments, fabrication processes to form a functional layer310 on the sidewall of the channel hole 300. The functional layer can bea composite dielectric layer, such as a combination of a barrier layer312, a storage layer 314, and a tunneling layer 316. The functionallayer 310, including the barrier layer 312, the storage layer 314, andthe tunneling layer 316, can be formed by one or more thin filmdeposition processes, such as ALD, CVD, PVD, any other suitableprocesses, or any combination thereof.

As shown in FIG. 3B, the barrier layer 312 can be formed between thestorage layer 314 and the sidewall of the channel hole 300. The barrierlayer 213 can be used for blocking the outflow of the electroniccharges. In some embodiments, the barrier layer 312 can be a siliconoxide layer or a combination of silicon oxide/silicon nitride/siliconoxide (ONO) layers. In some embodiments, the barrier layer 312 includeshigh dielectric constant (high-k) dielectrics (e.g., aluminum oxide). Insome embodiments, a thickness of the barrier layer 312 can be in a rangefrom about 3 nm to about 20 nm.

The storage layer 314 can be formed between the tunneling layer 316 andthe barrier layer 312. Electrons or holes from the channel layer cantunnel to the storage layer 314 through the tunneling layer 316. Thestorage layer 314 can be used for storing electronic charges (electronsor holes) for memory operation. The storage or removal of charge in thestorage layer 314 can impact the on/off state and/or a conductance ofthe semiconductor channel. The storage layer 314 can include one or morefilms of materials including, but are not limited to, silicon nitride,silicon oxynitride, a combination of silicon oxide and silicon nitride,or any combination thereof. In some embodiments, the storage layer 314can include a nitride layer formed by using one or more depositionprocesses. In some embodiments, a thickness of the storage layer 314 canbe in a range from about 3 nm to about 20 nm.

The tunneling layer 316 can be formed on the sidewall of the storagelayer 314. The tunneling layer 316 can be used for tunneling electroniccharges (electrons or holes). The tunneling layer 316 can includedielectric materials including, but not limited to, silicon oxide,silicon nitride, silicon oxynitride, or any combination thereof. In someembodiments, the tunneling layer 130 can be an oxide layer formed byusing a deposition process. In some embodiments, a thickness of thetunneling layer 316 can be in a range from about 3 nm to about 20 nm.

In some embodiments, fabrication processes to form the channel structurefurther include forming a channel layer 320 covering the sidewall of thefunctional layer 310. In some embodiments, the channel layer 320 can bean amorphous silicon layer or a polysilicon layer formed by using a thinfilm deposition process, such as ALD, CVD, PVD, or any other suitableprocess. In some embodiments, a thickness of the channel layer 320 canbe in a range from about 5 nm to 20 nm.

In some embodiments, fabrication processes to form the channel structurefurther include forming a filling structure 330 to cover the channellayer 320 and fill the channel hole 310. In some embodiments, thefilling structure 330 can be an oxide layer formed by using any suitabledeposition process, such as ALD, CVD, PVD, etc. In some embodiments, thefilling structure 330 can include one or more airgaps.

As shown in FIG. 2, the method proceeds to operation S6, in whichmultiple slits can be formed in the alternating dielectric stack. Asshown in FIG. 3C, each slit 400 can vertically penetrate through thealternating dielectric stack 200, and extend substantially in a straightline between two arrays of channel structures. The multiple slits 400can be formed by forming a mask layer over the alternating dielectricstack 200 and patterning the mask using, e.g., photolithography, to formopenings corresponding to the multiple slits in the patterned masklayer. A suitable etching process, e.g., dry etch and/or wet etch, canbe performed to remove portions of the alternating dielectric stack 200exposed by the openings until the multiple expose the substrate 100. Themask layer can be removed after the formation of the multiple slits.

As shown in FIG. 2, the method proceeds to operation S8, in which thesecond dielectric layers 220 in the alternating dielectric stack 200 canbe removed to form multiple trenches 410. The multiple trenches 410 canextend in a horizontal direction, and can be used as spaces for amulti-layer gate structure to be formed in the subsequent processes. Itis noted that, the term “horizontal/horizontally” used herein meansnominally parallel to a lateral surface of a substrate

As described above, the second dielectric layers 220 in the alternatingdielectric stack 200 are used as sacrificial layers, and are removed byused any suitable etching process, e.g., an isotropic dry etch or a wetetch. The etching process can have sufficiently high etching selectivityof the material of the second dielectric layers 220 over the materialsof the first dielectric layer 210, such that the etching process canhave minimal impact on the first dielectric layer 210. The isotropic dryetch and/or the wet etch can remove second dielectric layers 220 invarious directions to expose the top and bottom surfaces of each firstdielectric layer 210. As such, multiple horizontal trenches 410 can thenbe formed between first dielectric layers 210.

In some embodiments, the second dielectric layers 220 include siliconnitride and the etchant of the isotropic dry etch includes one or moreof CF₄, CHF₃, C4F₈, C4F₆, and CH₂F₂. The radio frequency (RF) power ofthe isotropic dry etch can be lower than about 100 W and the bias can belower than about 10V. In some embodiments, the second dielectric layers220 include silicon nitride and the etchant of the wet etch includesphosphoric acid.

After the second dielectric layers 220 are removed, the multiple slits400 and multiple trenches 410 can be cleaned by using any suitablecleaning process. For example, a phosphoric acid rinsing process can beperformed to remove the impurities on the inner wall of the trenches410. In some embodiments, a rinsing temperature can be in a range fromabout 100° C. to about 200° C., and a rinsing time can be in a rangefrom about 10 minutes to about 100 minutes. After the cleaning process,the top surfaces 212 and bottom surfaces 214 of the first dielectriclayers 210, and the outside sidewall portions of functional layers 310originally surrounded by the second dielectric layers 220 can be exposedthrough the multiple trenches 410.

As shown in FIG. 2, the method proceeds to operation S10, in which aninsulating layer can be formed in each of the multiple trenches 410. Theinsulating layer can be used as a gate dielectric layer for insulatingthe respective word line (i.e., gate electrode) formed in the subsequentprocesses from the adjacent first dielectric layer 212.

In some embodiments, the insulating layer can be formed by filling thehorizontal trenches 410 as shown in FIG. 3C with one or more suitableinsulating materials. For example, one or more suitable depositionprocesses, such as CVD, PVD, and/or ALD, can be utilized to deposit theone or more insulating materials into the horizontal trenches 410. Insome embodiments, a recess etch and/or a chemical-mechanicalplanarization (CMP) can be used to remove excessive insulatingmaterial(s) outside of the multiple trenches 410.

The one or more insulating materials can include any suitable materialsthat provide electric insulating function. For example, the one or moreinsulating materials can include silicon oxide, silicon nitride, siliconoxynitride, aluminum oxide, titanium nitride, etc., and/or any suitablecombinations thereof. In some embodiments, multiple insulating layerscan have different insulating materials.

In some embodiments, the insulating layer can have a laminatedstructure. For example, as shown in FIG. 3D, the insulating layer caninclude a first insulating sub-layer 510 covering the top surfaces 212and bottom surfaces 214 of the first dielectric layers 210, and theoutside sidewall portions of functional layers 310 that are exposed bythe multiple trenches 410. The insulating layer can further include asecond insulating sub-layer 520 covering the surfaces of the firstinsulating sub-layer 510. In some embodiments, the first insulatingsub-layer 510 can include high dielectric constant (high-k) dielectrics(e.g., aluminum oxide), and the second insulating sub-layer 520 caninclude titanium nitride as a glue layer to prevent following gateelectrode layers from peeling.

In some other embodiments, the insulating layer can be a single filmstructure. For example, the insulating layer can include a single high-kdielectric layer (e.g., titanium nitride film) covering the top surfaces212 and bottom surfaces 214 of the first dielectric layers 210, and theoutside sidewall portions of functional layers 310 that are exposed bythe multiple trenches 410. A thickness of the titanium nitride film canbe in a range from about 1 nm to about 10 nm.

As shown in FIG. 2, the method proceeds to operation S12, in which amulti-layer gate structure can be formed in the multiple trenches 410.The multi-layer gate structure can be formed by filling the horizontaltrenches 230 with a suitable gate electrode metal material. As shown inFIG. 3D, the gate electrode metal material can fill each horizontaltrench 410 to form a conductive layer 530 covering the insulating layer.The conductive layers 530 can provide the base material for thesubsequently-formed word lines (i.e., gate electrodes).

The gate electrode metal material can include any suitable conductivematerial, e.g., tungsten, aluminum, copper, cobalt, or any combinationthereof, for forming the word lines (i.e., gate electrodes). The gateelectrode material can be deposited into horizontal trenches 230 using asuitable deposition method such as CVD, physical vapor deposition (PVD),plasma-enhanced CVD (PECVD), sputtering, metal-organic chemical vapordeposition (MOCVD), and/or ALD. In some embodiments, the conductivelayers 530 include tungsten formed by CVD.

In some embodiments, after forming the multiple conductive layers 530,portions of the multiple conductive layers 530 can be removed. In someembodiments, in order to ensure the insulation between multiple gates, arecess etch can be performed to remove the portions of the multipleconductive layers 530 that are outside the multiple trenches 410 andclose to the multiple slits 400. In doing so, a recess of the conductivelayer 530 can be formed in each trench 410, as shown in FIG. 3E. Theremaining portions of the multiple conductive layers 530 can form themulti-layer gate structure, which includes multiple gates 540 each beingsandwiched by the insulating layer.

As shown in FIG. 2, the method proceeds to operation S14, in which afirst isolation layer can be formed on the sidewalls of the multipleslits 400. As shown in FIG. 3F, the first isolation layer 600 can coverthe sidewall of the slit 400, the exposed surfaces of the insulatinglayer, and the exposed surfaces of the multiple gates 540. The firstisolation layer 600 can be used to prevent the multiple gates 540 frombeing oxidized in the subsequent processes. In some embodiments, athickness of the first isolation layer 600 can be in a range from about0.1 nm to about 10 nm.

The first isolation layer 600 can be formed by depositing a materialincluding, but not limited to, silicon (e.g., polycrystalline silicon,monocrystalline silicon, or amorphous silicon), silicon nitride, siliconoxynitride, aluminum oxide, and/or any combination thereof. Thedepositing process can be CVD, sputtering, PVD, MOCVD, Low pressurechemical vapor deposition (LPCVD), polyatomic layer chemical vapordeposition (PLCVD), and/or ALD. Since the first isolation layer 600 isformed after the recess etching process of the multiple conductivelayers and has a comparatively small thickness, the first isolationlayer 600 also include multiple recesses corresponding to the multiplegates 540, as shown in FIG. 3F.

As shown in FIG. 2, the method proceeds to operation S16, in which asecond isolation layer can be formed on the sidewalls of the multipleslits 400. As shown in FIG. 3G, the second isolation layer 700 can coverthe first isolation layer 600. The second isolation layer 700 can beused to provide electrical insulation between the multiple gates 540 andconductive walls 800 formed in the subsequent process. The secondisolation layer 700 can be formed by a suitable deposition process and afollowing etching process. For example, a deposition process, such assputtering, PVD, MOCVD, Low pressure chemical vapor deposition (LPCVD),and/or ALD, etc., can be performed to form the second isolation layer700. A material of the second isolation layer 700 can include anysuitable insulating material that is different from the material of thefirst isolation layer 600, such as silicon oxide, etc.

It is noted that, in one embodiment, the first isolation layer 600 is asilicon film and the second isolation layer 700 is a silicon oxide film.In such case, during the deposition process to form the silicon oxidefilm, portions of or all of the silicon film can be oxidized to siliconoxide. Thus, portions of or all of the first isolation layer 600 can beconverted to the second isolation layer 700. That is, the formed siliconoxide layer can cover the sidewall of each slit 400, surfaces of theinsulating layer and the metal gate in each trench 410.

After the first isolation layer 600 and the second isolation layer 700are formed, an etching process can be performed to remove portions ofthe first isolation layer 600 and the second isolation layer 700 at thebottom of each slit 400 to expose the substrate 100. As such, secondisolation layer 700 can be formed on the sidewalls of the multiple slits400.

As shown in FIG. 2, the method proceeds to operation S18, in which aconductive wall can be formed in each of the multiple slits 400. Asshown in FIG. 3G, the conductive wall 800 can be sandwiched betweensecond isolation layers 700 in each slit 400. In some embodiments, theconductive wall 800 can be formed by depositing any suitable conductivematerial, such as metal materials including tungsten, aluminum, copper,polysilicon, silicides, and/or combinations thereof, etc. The conductivematerial can be deposited into slits 400 using a suitable depositionmethod such as CVD, physical vapor deposition (PVD), plasma-enhanced CVD(PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD),and/or ALD. In some embodiments, the conductive walls 800 includetungsten formed by CVD.

In some embodiments, before forming the conductive walls 800, dopedregions (not shown in figures) can be formed in the substrate 100 undereach slit 400 by, for example, ion implantation and/or thermal diffusionthrough the slits 400. After forming the multiple conductive walls, thelower end of each conductive wall 800 can be in contact with acorresponding doped region. It is understood that doped regions can beformed in an earlier fabrication stage, for example, prior to theformation of the multi-layer gate structure, according to someembodiments.

Accordingly, a method for forming a gate structure of a 3D memory deviceis provided in some embodiments in accordance with the presentdisclosure. In the disclosed method, after forming a multi-layer gatestructure, and before forming a silicon oxide layer on the sidewall ofslits, a silicon film can be formed to cover the exposed surfaces of themulti-layer gate structure to prevent the exposed surfaces of themulti-layer gate structure from being oxidized during the deposition ofthe silicon oxide layer. As such, a leakage between the multi-layer gatestructure and conductive wall in the slit can be eliminated, and aproduct yield of the 3D memory devices can be improved.

The method for forming a gate structure of a 3D memory device cancomprise: forming, on a substrate, an alternating dielectric stackincluding a plurality of dielectric layer pairs, each of the pluralityof dielectric layer pairs comprising a first dielectric layer and asecond dielectric layer different from the first dielectric layer;forming a plurality of slits, each penetrating vertically through thealternating dielectric stack and extending in a horizontal direction;removing the plurality of second dielectric layers in the alternatingdielectric stack through the plurality of slits to form a plurality oftrenches; forming a conductive layer in each of the plurality oftrenches; forming a first isolation layer on sidewalls of the pluralityof slits to cover the conductive layers to prevent the conductive layersfrom being oxidized; forming a second isolation layer on surfaces of thefirst isolation layer, a material of the second isolation layer beingdifferent from a material of the first isolation layer; and depositing aconductive material into the slits to form a plurality of conductivewalls, wherein the plurality of conductive walls are insulated from theconductive layers.

In some embodiments, each of the plurality of dielectric layer pairs isformed of a silicon oxide layer having a thickness in a range from about10 nm to about 150 nm and a silicon nitride layer having a thickness ina range from about 10 nm to about 150 nm.

In some embodiments, the method further comprises: forming a pluralityof channel structures, each penetrating vertically through thealternating dielectric stack; wherein each of the plurality of slitsextends horizontally between the plurality of channel structures.

In some embodiments, the method further comprises: after forming theplurality of slits, forming a plurality of doped regions below the slitsin the substrate, so as to contact each conductive wall with acorresponding doped region.

In some embodiments, the method further comprises: forming a filmincluding silicon, silicon nitride, silicon oxynitride, or aluminumoxide as the first isolation layer, a thickness of the film being in arange from about 0.1 nm to about 10 nm.

In some embodiments, the method further comprises: forming a siliconfilm as the first isolation layer; forming a silicon oxide film as thesecond isolation layer and; and oxidizing at least a portion of thesilicon film to silicon oxide during forming the second isolation layer.

In some embodiments, forming the plurality of channel structurescomprises: forming a channel hole extending vertically through thealternating dielectric stack; forming a functional layer on a sidewallof the channel hole; and forming a channel layer covering a sidewall ofthe functional layer.

In some embodiments, forming the functional layer comprises: forming abarrier layer on the sidewall of the channel hole for blocking anoutflow of the electronic charges; forming a storage layer on thesurface of the barrier layer for storing electronic charges duringoperation of the 3D memory device; and forming a tunneling layer on thesurface of the storage layer for tunneling electronic charges.

In some embodiments, the method further comprises: before forming theconductive layer in the plurality of trenches, forming an insulatinglayer in the plurality of trenches.

In some embodiments, forming the insulating layer comprises: forming afirst insulating sub-layer covering top surfaces and bottom surfaces ofthe plurality of first dielectric layers, and outside sidewall portionsof functional layers that are exposed by the plurality of trenches; andforming a second insulating sub-layer having a thickness in a range fromabout 1 nm to about 10 nm to cover the first insulating sub-layer.

In some embodiments, the first insulating sub-layer is formed bydepositing a first material including aluminum oxide; and the secondinsulating sub-layer is formed by depositing a second material includingtitanium nitride.

In some embodiments, the method further comprises: before forming theinsulating layer, performing a phosphoric acid rinsing process to cleanthe plurality of trenches, wherein a rinsing temperature of thephosphoric acid rinsing process is in a range from about 100° C. toabout 200° C., and a rinsing time of the phosphoric acid rinsing processis in a range from about 10 minutes to about 100 minutes.

In some embodiments, forming the conductive layer comprises: filling theplurality of trenches with a conductive material; and removing portionsof the conductive material to form a plurality of separated gates, eachof the plurality of separated gates being locating in a correspondingtrench.

In some embodiments, forming the first isolation layer comprises:performing a polyatomic layer chemical vapor deposition process or anatomic layer deposition process to form first isolation layer.

In some embodiments, forming the first isolation layer comprises:forming the first isolation layer to cover the sidewalls of theplurality of slits, exposed surfaces of the insulating layer, andexposed surfaces of the conductive layers.

In some embodiments, forming the first isolation layer comprises:forming the first isolation layer having a plurality of recesses, eachcorresponding to a separated gate.

In some embodiments, forming the alternating dielectric stack comprises:forming the alternating dielectric stack having a thickness larger than1000 nm in a vertical direction.

In some embodiments, forming the plurality of conductive wallscomprises: depositing a material including tungsten into the pluralityof slits to form the plurality of conductive walls.

Another aspect of the present disclosure provides a three-dimensional(3D) NAND memory device, comprising: an alternatingdielectric/conductive stack including a plurality ofdielectric/conductive layer pairs on a substrate, each of the pluralityof dielectric/conductive layer pairs comprising a dielectric layer and aconductive layer; a plurality of slits, each penetrating verticallythrough the alternating dielectric/conductive stack and extending in ahorizontal direction; a first isolation layer on sidewalls of theplurality of slits to cover the conductive layers to prevent theconductive layers from being oxidized; a second isolation layer onsurfaces of the first isolation layer, a material of the secondisolation layer being different from a material of the first isolationlayer; and a conductive wall sandwiched by the second isolation layer ineach slit, wherein the conductive wall is insulated from the conductivelayers of the alternating dielectric/conductive stack.

In some embodiments, each of the dielectric layer is a silicon oxidelayer having a thickness in a range from about 10 nm to about 150 nm;each of the conductive layer is a tungsten layer having a thickness in arange from about 10 nm to about 150 nm; and the conductive wall includestungsten.

In some embodiments, the device further comprises: a plurality ofchannel structures, each penetrating vertically through the alternatingdielectric/conductive stack; wherein each of the plurality of slitsextends horizontally between the plurality of channel structures.

In some embodiments, the device further comprises: a plurality of dopedregions below the slits in the substrate, wherein the conductive wall isin contact with a corresponding doped region in each slit.

In some embodiments, the first isolation layer is a film includingsilicon, silicon nitride, silicon oxynitride, or aluminum oxide; and thesecond isolation layer is a silicon oxide film.

In some embodiments, a thickness of the first isolation layer is in arange from about 0.1 nm to about 10 nm.

In some embodiments, each of the plurality of channel structurescomprises: a channel hole extending vertically through the alternatingdielectric/conductive stack; a functional layer on a sidewall of thechannel hole; and a channel layer covering a sidewall of the functionallayer.

In some embodiments, the functional layer comprises: a barrier layer onthe sidewall of the channel hole configured to block an outflow of theelectronic charges; a storage layer on the surface of the barrier layerconfigured to store electronic charges during operation of the 3D memorydevice; and a tunneling layer on the surface of the storage layerconfigured to tunnel electronic charges.

In some embodiments, the device further comprises: an insulating layerbetween the each dielectric layer and each conductive layer.

In some embodiments, the insulating layer is between the conductivelayers and the functional layer.

In some embodiments, the insulating layer comprises: a first insulatingsub-layer covering top surfaces and bottom surfaces of the plurality ofdielectric layers, and outside sidewall portions of functional layer;and a second insulating sub-layer covering the first insulatingsub-layer and having a thickness in a range from about 1 nm to about 10nm.

In some embodiments, the first insulating sub-layer includes aluminumoxide; and the second insulating sub-layer includes titanium nitride.

In some embodiments, the first isolation layer having a plurality ofrecesses, each corresponding to a conductive layer sandwiched betweentwo dielectric layers.

In some embodiments, the alternating dielectric/conductive stack has atleast 64 dielectric/conductive layer pairs and has a thickness largerthan 1000 nm in a vertical direction.

The foregoing description of the specific embodiments will so fullyreveal the general nature of the present disclosure that others can, byapplying knowledge within the skill of the art, readily modify and/oradapt for various applications such specific embodiments, without undueexperimentation, without departing from the general concept of thepresent disclosure. Therefore, such adaptations and modifications areintended to be within the meaning and range of equivalents of thedisclosed embodiments, based on the teaching and guidance presentedherein. It is to be understood that the phraseology or terminologyherein is for the purpose of description and not of limitation, suchthat the terminology or phraseology of the present specification is tobe interpreted by the skilled artisan in light of the teachings andguidance.

Embodiments of the present disclosure have been described above with theaid of functional building blocks illustrating the implementation ofspecified functions and relationships thereof. The boundaries of thesefunctional building blocks have been arbitrarily defined herein for theconvenience of the description. Alternate boundaries can be defined solong as the specified functions and relationships thereof areappropriately performed.

The Summary and Abstract sections may set forth one or more but not allexemplary embodiments of the present disclosure as contemplated by theinventor(s), and thus, are not intended to limit the present disclosureand the appended claims in any way.

The breadth and scope of the present disclosure should not be limited byany of the above-described exemplary embodiments, but should be definedonly in accordance with the following claims and their equivalents.

What is claimed is:
 1. A method for forming a three-dimensional (3D)NAND memory device, comprising: forming, on a substrate, an alternatingdielectric stack including a plurality of dielectric layer pairs, eachof the plurality of dielectric layer pairs comprising a first dielectriclayer and a second dielectric layer different from the first dielectriclayer; forming a plurality of slits, each penetrating vertically throughthe alternating dielectric stack and extending in a horizontaldirection; removing the plurality of second dielectric layers in thealternating dielectric stack through the plurality of slits to form aplurality of trenches; forming a conductive layer in each of theplurality of trenches; forming a first isolation layer on sidewalls ofthe plurality of slits to cover the conductive layers to prevent theconductive layers from being oxidized; forming a second isolation layeron surfaces of the first isolation layer, a material of the secondisolation layer being different from a material of the first isolationlayer; and depositing a conductive material into the slits to form aplurality of conductive walls, wherein the plurality of conductive wallsare insulated from the conductive layers.
 2. The method of claim 1,further comprising: after forming the plurality of slits, forming aplurality of doped regions below the slits in the substrate, so as tocontact each conductive wall with a corresponding doped region.
 3. Themethod of claim 1, further comprising: forming a film including silicon,silicon nitride, silicon oxynitride, or aluminum oxide as the firstisolation layer, a thickness of the film being in a range from about 0.1nm to about 10 nm.
 4. The method of claim 1, further comprising: forminga silicon film as the first isolation layer; forming a silicon oxidefilm as the second isolation layer and; and oxidizing at least a portionof the silicon film to silicon oxide during forming the second isolationlayer.
 5. The method of claim 1, further comprising: before forming theconductive layer in the plurality of trenches, forming an insulatinglayer in the plurality of trenches.
 6. The method of claim 5, whereinforming the insulating layer comprises: forming a first insulatingsub-layer covering top surfaces and bottom surfaces of the plurality offirst dielectric layers, and outside sidewall portions of functionallayers that are exposed by the plurality of trenches; and forming asecond insulating sub-layer having a thickness in a range from about 1nm to about 10 nm to cover the first insulating sub-layer.
 7. The methodof claim 6, wherein: the first insulating sub-layer is formed bydepositing a first material including aluminum oxide; and the secondinsulating sub-layer is formed by depositing a second material includingtitanium nitride.
 8. The method of claim 5, further comprising: beforeforming the insulating layer, performing a phosphoric acid rinsingprocess to clean the plurality of trenches, wherein a rinsingtemperature of the phosphoric acid rinsing process is in a range fromabout 100° C. to about 200° C., and a rinsing time of the phosphoricacid rinsing process is in a range from about 10 minutes to about 100minutes.
 9. The method of claim 1, wherein forming the conductive layercomprises: filling the plurality of trenches with a conductive material;and removing portions of the conductive material to form a plurality ofseparated gates, each of the plurality of separated gates being locatingin a corresponding trench.
 10. The method of claim 5, wherein formingthe first isolation layer comprises: forming the first isolation layerto cover the sidewalls of the plurality of slits, exposed surfaces ofthe insulating layer, and exposed surfaces of the conductive layers,wherein the first isolation layer has a plurality of recesses, eachrecess corresponding to a separated gate.
 11. A three-dimensional (3D)NAND memory device, comprising: an alternating dielectric/conductivestack including a plurality of dielectric/conductive layer pairs on asubstrate, each of the plurality of dielectric/conductive layer pairscomprising a dielectric layer and a conductive layer; a plurality ofslits, each penetrating vertically through the alternatingdielectric/conductive stack and extending in a horizontal direction; afirst isolation layer on sidewalls of the plurality of slits to coversurfaces of the conductive layers adjacent to the slits to prevent theconductive layers from being oxidized; a second isolation layer onsurfaces of the first isolation layer, a material of the secondisolation layer being different from a material of the first isolationlayer; and a conductive wall sandwiched by the second isolation layer ineach slit, wherein the conductive wall is insulated from the conductivelayers of the alternating dielectric/conductive stack.
 12. The device ofclaim 11, further comprising: a plurality of doped regions below theslits in the substrate, wherein the conductive wall is in contact with acorresponding doped region in each slit.
 13. The device of claim 11,wherein: the first isolation layer is a film including silicon, siliconnitride, silicon oxynitride, or aluminum oxide; and the second isolationlayer is a silicon oxide film.
 14. The device of claim 13, wherein: athickness of the first isolation layer is in a range from about 0.1 nmto about 10 nm.
 15. The device of claim 11, wherein each of theplurality of channel structures comprises: a channel hole extendingvertically through the alternating dielectric/conductive stack; afunctional layer on a sidewall of the channel hole; and a channel layercovering a sidewall of the functional layer.
 16. The device of claim 15,wherein the functional layer comprises: a barrier layer on the sidewallof the channel hole configured to block an outflow of the electroniccharges; a storage layer on the surface of the barrier layer configuredto store electronic charges during operation of the 3D memory device;and a tunneling layer on the surface of the storage layer configured totunnel electronic charges.
 17. The device of claim 16, furthercomprising: an insulating layer between the each dielectric layer andeach conductive layer.
 18. The device of claim 17, wherein theinsulating layer comprises: a first insulating sub-layer covering topsurfaces and bottom surfaces of the plurality of dielectric layers, andoutside sidewall portions of functional layer; and a second insulatingsub-layer covering the first insulating sub-layer and having a thicknessin a range from about 1 nm to about 10 nm.
 19. The device of claim 18,wherein: the first insulating sub-layer includes aluminum oxide; and thesecond insulating sub-layer includes titanium nitride.
 20. The device ofclaim 11, wherein: the first isolation layer having a plurality ofrecesses, each corresponding to a conductive layer sandwiched betweentwo dielectric layers.